4 ms·

Given this poor scaling maybe we will see some CPUs like AMD's Milan-X but taken to the next level: - Remove all or almost all L3 from the CPU die built with t

Given this poor scaling maybe we will see some CPUs like AMD's Milan-X but taken to the next level: - Remove all or almost all L3 from the CPU die built with the best available logic process, like N3E - Stack a last level cache die with relatively cheaper process that has similar or better SRAM density, like N5

AnthonyMouse 4y ago
Adding more levels of cache is a time-honored tradition, and it works. For example, with the M1, Apple tied the DRAM interface to the CPU. That got them more bandwidth, but then you can't upgrade the memory, which is weak. But why not do both? Have e.g. 8GB of high-bandwidth DRAM soldered to the board, essentially that amount of L4 cache, but keep the DIMM slots where you can add arbitrarily more memory with less bandwidth.
- Palomides 4y ago
  later Xeon Phi chips had this, 16GB of on-package RAM with 4x the bandwidth of the external RAM
  - fulafel 4y ago
    IBM has been doing this for a long time. Eg here's one mainframe CPU with 960 MB of L4: https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edram-density-adds-hundreds-of-megabytes-of-cache/ https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edr... (They also have DRAM in other levels of cache hierarchy except L1, with L2 running at 5+ GHz)
- legulere 4y ago
  There’s potentially even more layers. Compute express link allows to expand the system with even more RAM slowly through PCIe And already now you have NUMA where performance is different and depending on which core you are.
- Vogtinator 4y ago
  IBM are the masters of this: https://www.anandtech.com/show/16924/did-ibm-just-preview-the-future-of-caches https://www.anandtech.com/show/16924/did-ibm-just-preview-th... Processors can use the L2 cache from other (remote) processors before reaching out to DRAM.
- Tuna-Fish 4y ago
  It adds latency. You have to probe all the earlier levels of the cache before you can access the next one, if you want the caches to help with bandwidth. The cost of probing more levels adds up.

AnthonyMouse 4y ago

Adding more levels of cache is a time-honored tradition, and it works. For example, with the M1, Apple tied the DRAM interface to the CPU. That got them more bandwidth, but then you can't upgrade the memory, which is weak. But why not do both? Have e.g. 8GB of high-bandwidth DRAM soldered to the board, essentially that amount of L4 cache, but keep the DIMM slots where you can add arbitrarily more memory with less bandwidth.

Palomides 4y ago
later Xeon Phi chips had this, 16GB of on-package RAM with 4x the bandwidth of the external RAM
- fulafel 4y ago
  IBM has been doing this for a long time. Eg here's one mainframe CPU with 960 MB of L4: https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edram-density-adds-hundreds-of-megabytes-of-cache/ https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edr... (They also have DRAM in other levels of cache hierarchy except L1, with L2 running at 5+ GHz)
legulere 4y ago
There’s potentially even more layers. Compute express link allows to expand the system with even more RAM slowly through PCIe And already now you have NUMA where performance is different and depending on which core you are.
Vogtinator 4y ago
IBM are the masters of this: https://www.anandtech.com/show/16924/did-ibm-just-preview-the-future-of-caches https://www.anandtech.com/show/16924/did-ibm-just-preview-th... Processors can use the L2 cache from other (remote) processors before reaching out to DRAM.
Tuna-Fish 4y ago
It adds latency. You have to probe all the earlier levels of the cache before you can access the next one, if you want the caches to help with bandwidth. The cost of probing more levels adds up.