"We now pause all CPU activity as we refresh the DRAM for all the registers.. " - sheesh! That's not going to happen because the process tech for dram is tuned

"We now pause all CPU activity as we refresh the DRAM for all the registers.. " - sheesh! That's not going to happen because the process tech for dram is tuned for capacitance and the process tech for SRAM and CPUs is tuned for speed... How about, "this CPU is using 3D nandram and is rated only for one quadrillion instructions or one year whichever one comes first!" Imagine a compiler that has to do wear-leveling on the registers!