3 ms·
This would benefit sequential access, but it'd either be disabled for random-access or pollute the caches with unused lines. But in cases where sequential memo
by iamchp 4y ago
This would benefit sequential access, but it'd either be disabled for random-access or pollute the caches with unused lines.
But in cases where sequential memory bandwidth is required, this is pretty cool!
(But I assume Intel only, which would also be a bummer)