At least on the K6 this was implemented in a really neat way. Reusing most of the hardware for CPU exceptions, the store buffers and the instruction queues com

At least on the K6 this was implemented in a really neat way. Reusing most of the hardware for CPU exceptions, the store buffers and the instruction queues communicated and would perform most of the work rolling back state, and then instead of jumping through the IDT and pushing the first bit of exception state onto the stack, it just jumps directly to the next instruction after the rolled back state.