Yes. The logic is (slightly simplified): if the first cycle of an instruction then load opcode directly into the microcode address else if short jump then updat

Yes. The logic is (slightly simplified): if the first cycle of an instruction then load opcode directly into the microcode address else if short jump then update 4 low bits of the microcode address else if long jump or subroutine call then load microcode address from translation ROM else if subroutine return then load microcode address from pushed address else increment the microcode address to the next instruction. (This is implemented in hardware with a multiplexer, not as sequential if-then-else instructions.) There's no decoding logic between the opcode in the instruction register and the microcode address. So yes, the opcode bits are the index into the microcode ROM. rep_lodsb covered a lot of the instruction handling in the sibling comment. I hope to write a part 2 before too long.