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Another really amazing article! I had a few questions: Does a CPU's decoder circuit connect directly to this ROM then? If so is it connection to the translati

Another really amazing article! I had a few questions: Does a CPU's decoder circuit connect directly to this ROM then? If so is it connection to the translation ROM? The second question I had was regarding the the image used to demonstrate the CORD routine. What are the microinstructions that don't have an address or a source and destination such as NCY, LRCY and RCY? Lastly the author states: >"Surprisingly, there's no specific "microcode decoder" circuit. Instead, the logic is scattered across the chip, looking for various microcode bit patterns to generate control signals where they are needed." Could you elaborate on this? What is meant by "looking for various microcode bit patterns to generate control signals where they are needed"? What exactly is the thing that is doing the looking here? I feel like this is an important point but I am unable to understand it.

kens 4y ago
> Does a CPU's decoder circuit connect directly to this ROM then? If so is it connection to the translation ROM? The microcode address register loads the instruction opcode directly as the microcode address. For a microcode long jump or subroutine call, the microcode address is loaded from the Translation ROM. So you can think of the Translation ROM as a table of addresses for special cases. > The second question I had was regarding the the image used to demonstrate the CORD routine. What are the microinstructions that don't have an address or a source and destination such as NCY, LRCY and RCY? I wanted to focus on the hardware for this post, so I didn't go into a lot of detail on the micro-instructions. NCY is "jump if not carry" (i.e. the carry flag is not set). "NCY 7" does a jump to line 7. "LRCY tmpc" is "left rotate through carry the value in temporary register c". RCY is "reset carry". You can sort of see how it's performing a divide through a loop of shifts and subtracts. > What is meant by "looking for various microcode bit patterns to generate control signals where they are needed"? What exactly is the thing that is doing the looking here? I feel like this is an important point but I am unable to understand it. Well, I'm not sure if it is important, but I found it interesting :-) My point was that you might expect the micro-instructions to go through a block of decoding circuitry that generates the control signals for the processor. Instead, various bits from the micro-instruction go all over the processor. There are gates scattered all over that match on patterns such as if bit 3 is set AND bit 4 is clear AND bit 5 is set then do something like load a register. So the decoding logic is ad hoc and extremely distributed. There are some decoding blocks that are more structured, such a turning the micro-instruction's ALU bits into ALU control lines, but these blocks are also scattered across the chip. Hopefully this all makes sense. Let me know if you'd like me to elaborate.
- bogomipz 4y ago
  Thanks for the clarifications. I think I may have articulated my first question poorly. What I mean to ask is how does the CPU's decoder circuit interface with the Microcode ROM? It sounds as though the opcode bits are basically an index into the microcode ROM? >"I wanted to focus on the hardware for this post, so I didn't go into a lot of detail on the micro-instructions." Understood. I hope this means we can look forward to a part 2 then! There is really a lot fascinating things here.
  - rep_lodsb 4y ago
    The ROM has 13 address bits: 8 from the opcode, an extra one that is clear for normal opcodes and set for internal subroutines, and 4 bits for the microcode instruction counter. However some of the address bits are ignored, for example anything that matches the bit pattern 00xxx0xx is some kind of ALU operation, either between two registers, or a register and memory. The 3 bits in the middle select the operation, the low bit the operand size (byte or word), and the second one the direction (which operand is in memory, if any - with two register operands both encodings can be used). All of this extra information is decoded by random logic. The microcode for this class of opcodes looks like this (in one representation anyway, not necessarily the most easy to understand but based on the patent): M -> tmpa 1 XI tmpa R -> tmpb 4 none WB,NX SIGMA -> M 4 none RNI F 6 W DD,P0 On the left are the register moves: M is the first/destination operand, and R the second one. SIGMA (Σ in the patent) is the output from the ALU. The first line of code on the right sets up the ALU ("type 1 instruction" XI: select ALU operation from opcode bits; first operand in tmpa, second one is always tmpb). The next one prepares to write back the result and decode the next instruction. If the result goes to a register, the third line will be the last one executed ("type 4", RNI: run next instruction; F: update flag register). If it goes to memory, the store happens on the fourth line ("type 6", write, default data segment, no auto-increment). You can find more information in the linked patent (US4449184) and blog post (https://www.reenigne.org/blog/8086-microcode-disassembled https://www.reenigne.org/blog/8086-microcode-disassembled)
  - kens 4y ago

kens 4y ago

> Does a CPU's decoder circuit connect directly to this ROM then? If so is it connection to the translation ROM? The microcode address register loads the instruction opcode directly as the microcode address. For a microcode long jump or subroutine call, the microcode address is loaded from the Translation ROM. So you can think of the Translation ROM as a table of addresses for special cases. > The second question I had was regarding the the image used to demonstrate the CORD routine. What are the microinstructions that don't have an address or a source and destination such as NCY, LRCY and RCY? I wanted to focus on the hardware for this post, so I didn't go into a lot of detail on the micro-instructions. NCY is "jump if not carry" (i.e. the carry flag is not set). "NCY 7" does a jump to line 7. "LRCY tmpc" is "left rotate through carry the value in temporary register c". RCY is "reset carry". You can sort of see how it's performing a divide through a loop of shifts and subtracts. > What is meant by "looking for various microcode bit patterns to generate control signals where they are needed"? What exactly is the thing that is doing the looking here? I feel like this is an important point but I am unable to understand it. Well, I'm not sure if it is important, but I found it interesting :-) My point was that you might expect the micro-instructions to go through a block of decoding circuitry that generates the control signals for the processor. Instead, various bits from the micro-instruction go all over the processor. There are gates scattered all over that match on patterns such as if bit 3 is set AND bit 4 is clear AND bit 5 is set then do something like load a register. So the decoding logic is ad hoc and extremely distributed. There are some decoding blocks that are more structured, such a turning the micro-instruction's ALU bits into ALU control lines, but these blocks are also scattered across the chip. Hopefully this all makes sense. Let me know if you'd like me to elaborate.

bogomipz 4y ago
Thanks for the clarifications. I think I may have articulated my first question poorly. What I mean to ask is how does the CPU's decoder circuit interface with the Microcode ROM? It sounds as though the opcode bits are basically an index into the microcode ROM? >"I wanted to focus on the hardware for this post, so I didn't go into a lot of detail on the micro-instructions." Understood. I hope this means we can look forward to a part 2 then! There is really a lot fascinating things here.
- rep_lodsb 4y ago
  The ROM has 13 address bits: 8 from the opcode, an extra one that is clear for normal opcodes and set for internal subroutines, and 4 bits for the microcode instruction counter. However some of the address bits are ignored, for example anything that matches the bit pattern 00xxx0xx is some kind of ALU operation, either between two registers, or a register and memory. The 3 bits in the middle select the operation, the low bit the operand size (byte or word), and the second one the direction (which operand is in memory, if any - with two register operands both encodings can be used). All of this extra information is decoded by random logic. The microcode for this class of opcodes looks like this (in one representation anyway, not necessarily the most easy to understand but based on the patent): M -> tmpa 1 XI tmpa R -> tmpb 4 none WB,NX SIGMA -> M 4 none RNI F 6 W DD,P0 On the left are the register moves: M is the first/destination operand, and R the second one. SIGMA (Σ in the patent) is the output from the ALU. The first line of code on the right sets up the ALU ("type 1 instruction" XI: select ALU operation from opcode bits; first operand in tmpa, second one is always tmpb). The next one prepares to write back the result and decode the next instruction. If the result goes to a register, the third line will be the last one executed ("type 4", RNI: run next instruction; F: update flag register). If it goes to memory, the store happens on the fourth line ("type 6", write, default data segment, no auto-increment). You can find more information in the linked patent (US4449184) and blog post (https://www.reenigne.org/blog/8086-microcode-disassembled https://www.reenigne.org/blog/8086-microcode-disassembled)
- kens 4y ago