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> Your suggestion that AMD used 16 ALUs per pipe under VLIW is wrong, The change is 4/5 VLIW ALUs to 16 ALUs that now can execute SIMD instructions. Actually,
by Tuna-Fish 15y ago
> Your suggestion that AMD used 16 ALUs per pipe under VLIW is wrong, The change is 4/5 VLIW ALUs to 16 ALUs that now can execute SIMD instructions.
Actually, the previous architecture was a setup of 16x simd, where each of the simd operations was a 5/4 wide vliw. So calling that 320 hardware threads is wrong -- in Cypress there really was only 20 front-ends which drove these bundles of 80 alus in groups of 5x16. Also, it was a 4-long barrel processor, so you had to schedule a SIMD "wavefront" of 64 "threads" for each unit.
In the new version each CU still has 4x16 ALUS like it had in Cayman, but now each of the 4 simd units of 16 elements can be scheduled independently by a different hardware thread.
- DiabloD3 15y agoThere are 20 CUs, but it controls multiple sets of VLIW5/4 in parallel. AMD claims 1600 ALUs on the 5870, so 1600/5 = 320. I'm not sure how they are are factoring in the 4 deep pipeline for the barrel, but I'm pretty sure it doesn't mean there is only 80 actual ALUs. The R700 Programming Manual seems to indicate my interpretation is correct, although if you can provide evidence that I'm misinterpreting it, I'm all ears.
- Tuna-Fish 15y agoThere are 1600 Alus, but they are grouped in vliws of 5 elements, which are grouped in simd groups of 16 vliws. So there are 20 front ends, and reading a single bundle in one of them will instantly make 80 alus execute an instruction. The barrel is essentially used to extend the vector registers from 16-elem to 64-elem, and a 64 "thread" wavefront, consisting of 5 VLIW'd instructions is essentially the smallest amount of work that R700 can do.