4 ms·
On Apple silicon, there's a fun new twist: the instruction (I) and data (D) caches are separate, so you have to remember to call sys_icache_flush [1] to keep th
by mkeeter 4y ago
On Apple silicon, there's a fun new twist: the instruction (I) and data (D) caches are separate, so you have to remember to call sys_icache_flush [1] to keep them in sync!
If you don't handle this correctly, then you'll have a Very Fun time [2].
What's especially Fun is that if you halt your program in a debugger and read back the contents of the JIT buffer, it will look perfectly correct – because those reads are coming through RAM / DCache, not ICache!
[1] https://developer.apple.com/library/archive/documentation/System/Conceptual/ManPages_iPhoneOS/man3/sys_icache_invalidate.3.html https://developer.apple.com/library/archive/documentation/Sy...
[2] https://twitter.com/impraxical/status/1579586601117548544 https://twitter.com/impraxical/status/1579586601117548544
- moonchild 4y agoArm, rather, and many other architectures besides. Even x86 does not guarantee complete I/D cache coherency (although its guarantees are much stronger than arm's).
- saagarjha 4y agoIt doesn't? Pretty sure this is true…
- moonchild 4y agox86? Yes, coherence is basically at the level of traces. If you modify some code and then jump to it, you're guaranteed to get the new code; but if you modify some code within a currently running trace, the results are unspecified. E: see the intel SDM, vol 3, sec 8.1.3.
- saagarjha 4y agoAh, I see. Thanks!