4 ms·
Why would x86 L1 be limited by the page size? The cache works at 128 byte granularity. If it's too big it might increase tlb pressure I suppose, but it makes se
by muricula 4y ago
Why would x86 L1 be limited by the page size? The cache works at 128 byte granularity. If it's too big it might increase tlb pressure I suppose, but it makes sense that increases in L1 would be best accompanied by increases in tlb size.
- gpderetta 4y agoIt is a quirk of VIPT caches. After a certain point you can't increase index size, only ways and quickly reach diminishing returns. There might be of course workarounds, but intel L1 cache sizes have been more or less stable for about a decade
- mbitsnbites 4y agoI believe that ARM has a patent on a workaround. Apple M1 has 192KB L1I.
- gpderetta 4y agoApple has a larger page size though.