4 ms·
The "Network transfer speed / cost." issue was worse than this make it seem. In the first CISC designs you were reading in the instruction one byte at a time o
by Symmetry 4y ago
The "Network transfer speed / cost." issue was worse than this make it seem. In the first CISC designs you were reading in the instruction one byte at a time over the same bus that you would use to load or store data. An extra byte in the instruction meant that the instruction took an extra cycle to complete.
- bell-cot 4y ago> ...In the first CISC designs... In the x86 world, this issue applied all the way through the 80386 CPU. Or through the 80486, if you're a bit harsher in judging it's unified (code + data) 8KB cache*. (True, not one byte at a time once you got to the 8086. But the 32-bit 80386 and 80486 only had 32-bit busses, and those were still serious bottlenecks.) *The cache was "write-through" on all but a very few variants, yielding extra congestion on the bus.