There's zero microcode. You can go into the StrongARM period and beyond before you're hitting anything like microcode. It's anathema to the basis of RISC CPUs.

There's zero microcode. You can go into the StrongARM period and beyond before you're hitting anything like microcode. It's anathema to the basis of RISC CPUs. IIRC, you'll only start finding it when there's a need to emulate earlier ISAs.