5 ms·

Yes, they theoretically could. The AMD manual contains this language: Exception and trap behavior for elements not selected for loading or storing from/to memo

by janwas 4y ago

Yes, they theoretically could. The AMD manual contains this language: Exception and trap behavior for elements not selected for loading or storing from/to memory is implementation dependent. For instance, a given implementation may signal a data breakpoint or a page fault for doublewords that are zero-masked and not actually written.

p0nce 4y ago
Well this makes the instruction useless unless all memory pointed to makes no page fault.
- janwas 4y ago
  Agreed. This is why it is even more important for the application to pad its arrays to the vector size. Then we might also skip the masking entirely.
  - p0nce 4y ago
    Yes. It also makes the masked instruction more portable to arm or non-x86, which is great. It also avoids the side channel?
p0nce 4y ago
Oh god it's worse than expected: https://erik.science/2019/06/21/AVX-fun.html https://erik.science/2019/06/21/AVX-fun.html
- janwas 4y ago
  Interesting, hadn't seen this before. So it's another side channel, one of many.