While that is true, and AMD CPUs are even worse thanks to chiplets, the latency and bandwidth of the inter-chip cache coherent interconnect is a lot worse than

While that is true, and AMD CPUs are even worse thanks to chiplets, the latency and bandwidth of the inter-chip cache coherent interconnect is a lot worse than the on-chip (or on-socket in AMD's case) buses. That is the expensive part of it. Cache line sharing (false and true sharing) still hurts in 1S configurations, but it hurts a lot less.