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Am I right that this is all simulated in software? I mean for the "implemented on FPGA" part, is there a physical FPGA running this OS? If so, how does it talk
by bo1024 4y ago
Am I right that this is all simulated in software? I mean for the "implemented on FPGA" part, is there a physical FPGA running this OS? If so, how does it talk to the rest of the computer (i.e. drivers, etc)?
- aewens 4y ago> A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence the term field-programmable. > FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together. Logic blocks can be configured to perform complex combinational functions, or act as simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.[1] Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigurable computing as performed in computer software. The above being from the FPGA Wikipedia page[0]. So yes, it is done “in software”, but FPGAs is fancy hardware that can reprogrammed to act as new hardware on the fly using software. Many are implemented as PCI devices, so they could interact with the rest of the system over the PCI bus. [0] https://en.m.wikipedia.org/wiki/Field-programmable_gate_array https://en.m.wikipedia.org/wiki/Field-programmable_gate_arra...
- bo1024 4y agoSorry, my question wasn't clear. What I am asking is whether the FPGA was being simulated in a VM, or whether the OS they built was running on a physical FPGA. And if the latter, how did the OS handle drivers for other components.
- VLM 4y agoApparently simulated. You can see in the UART code for example: https://github.com/nyuichi/GAIA3/blob/master/hardware/Rx.vhd https://github.com/nyuichi/GAIA3/blob/master/hardware/Rx.vhd file input_file : ft open READ_MODE is input_filename; read(input_file, c); data <= std_logic_vector(to_unsigned(character'pos(c), 8)); And so on and so forth, to pump a file on the simulation PC into a VHDL logic array one byte at a time as a simulation of a UART. Would be pretty funny if the above is the "wrong" repo for the story, but it is at least "an implementation" of the GAIA architecture, if not "the implementation" from the story.
- magicalhippo 4y agoThe original Xv6 code uses the x86 IO ports for example[1][2][3], it would be easy to implement something similar for the soft CPU I imagine. Some good info about IO ports in the answers to this[4] SO question. [1]: https://github.com/mit-pdos/xv6-public/blob/eeb7b415dbcb12cc362d0783e41c3d1f44066b17/console.c#L132 https://github.com/mit-pdos/xv6-public/blob/eeb7b415dbcb12cc... [2]: https://github.com/mit-pdos/xv6-public/blob/eeb7b415dbcb12cc362d0783e41c3d1f44066b17/x86.h#L22 https://github.com/mit-pdos/xv6-public/blob/eeb7b415dbcb12cc... [3]: https://www.felixcloutier.com/x86/out https://www.felixcloutier.com/x86/out [4]: https://stackoverflow.com/questions/3215878/what-are-in-out-instructions-in-x86-used-for https://stackoverflow.com/questions/3215878/what-are-in-out-...
- LoganDark 4y agoTheir software simulator was built to allow the porting process, but as far as I can tell, they did implement their design on a physical FPGA, yes.