4 ms·
Modern x86 CPUs typically have three layers of caching, where L1 and L2 are per-core, and only L3 is shared across all cores. You still have to solve all the ca
by pdpi 4y ago
Modern x86 CPUs typically have three layers of caching, where L1 and L2 are per-core, and only L3 is shared across all cores. You still have to solve all the cache coherency issues, and everything in the article still applies, even with just one socket.
- pclmulqdq 4y agoWhile that is true, and AMD CPUs are even worse thanks to chiplets, the latency and bandwidth of the inter-chip cache coherent interconnect is a lot worse than the on-chip (or on-socket in AMD's case) buses. That is the expensive part of it. Cache line sharing (false and true sharing) still hurts in 1S configurations, but it hurts a lot less.