> I understand the errata well enough, it implies that the processor state is indeterminate between the segment assignment and subsequent update to SP. The roo

> I understand the errata well enough, it implies that the processor state is indeterminate between the segment assignment and subsequent update to SP. The root cause was effectively a bug in the programming model, not in the implementation -- there was no way to atomically relocate the stack (by updating SS and SP). The processor state wasn't indeterminate between the two instructions that updated SS and SP, but the behavior resulting from an interrupt at that point would almost certainly be unintended, since the CPU would push state onto a stack in the wrong location, potentially overwriting other stack frames, and the architecture as originally designed provided no way to prevent this.