"Cycles per instruction" sounds more like a measurement of instruction latency rather than instruction throughput, and I don't think instruction latency has imp

"Cycles per instruction" sounds more like a measurement of instruction latency rather than instruction throughput, and I don't think instruction latency has improved as much in the past decade as instruction throughput: the most significant microarchitecture trend has been toward wider CPUs with more execution ports, wider instruction decoders, and larger reorder buffers.