RDNA3 has memory/cache chiplets providing 3.5Tbps. The 0.9Tbps of much further distance chip to chip conmevtivity here is highly impressive. Interesting to note

RDNA3 has memory/cache chiplets providing 3.5Tbps. The 0.9Tbps of much further distance chip to chip conmevtivity here is highly impressive. Interesting to note that RDNA3 links are only 10Gbps, they just have extreme interposer design with hundreds upon hundreds of incredibly small wires (resulting in stupendously high bit-efficiency); not something a multi-GPU design can do, and hence Nvidia doing 100Gbps links. Given where ethernet is (on the way to terabit ethernet) Im not surprised Nvidia is here, but it's still cool to see. The onboard SHARP processor on the NVswitch is very cool to read about. Given how much ML involves crunching many matrixes/tensors then adding the results, being able to parallelize the crunching and have a central aggregator makes sense. In general I hope we see an emerging presence of extremely high-fabric connectivity cpus & gpus that can serve as DPUs like this, as central coordinators. Thinking of this less as a switch (which it certainly is too, with it's vast bank of PHYs and massive crossbar) but more as an io cemtric computer is, I think, deserved.