4 ms·

Nope! Man, there are a lot of people in the comments who didn't read it.

• rkalla 15y ago
  wait, I thought that was the reason? (the L1-cache misses)
  • jbri 15y ago
    It is due to CPU cache issues, but not because the cache is full. CPU caches are indexed on the low bits of the address. If you have two addresses with the same low-order bits, then those addresses will collide in the cache, even though the cache isn't full. Large allocations (e.g. huge arrays) tend to get their own memory pages allocated - which means that the same offset in two different arrays ends up having the same low-order bits.
  • beagle3 15y ago
    No. It's cache misses, but because of cache-line hash collisions (multiple inputs consistently clash on the same cache line; when it's only 2 inputs, in that specific CPU, they all fit in L1, when it's 4, they don't -- regardless of the cache size; this case is tripped by the associativity)