3 ms·
tl;dr: At small scales, efficiency is dominated by loop overhead. At larger scales, issues of cache size and bus bandwidth come to dominate. (In particular, i
by blahedo 15y ago
tl;dr: At small scales, efficiency is dominated by loop overhead. At larger scales, issues of cache size and bus bandwidth come to dominate. (In particular, if the memory accessed in the single loop doesn't all fit in the cache at once, the two loops might be faster if their respective portions of memory each can fit in the cache.)
- kenferry 15y agoActually, it turned out to be more interesting than that. False tldr! It had to do with the way the cache is addressed - just shifting one or the other array over in memory so all the parallel indexes weren't at the same offset from the beginning of the cache line would address it.