3 ms·
The extension is putting Intel-compatible parity and adjust / aux carry flags in (architecturally zero) bits 26 and 27 of the ARM flags (NCZV) register, to avoi
by mananaysiempre 4y ago
The extension is putting Intel-compatible parity and adjust / aux carry flags in (architecturally zero) bits 26 and 27 of the ARM flags (NCZV) register, to avoid the ahead-of-time translator that is Rosetta 2 having to defensively compute them when it can’t tell they’re unused. No information on how to enable that extension.
- ehutch79 4y agoIt's probably a bad idea to enable this for your own use. I would bet real money that this goes away with the generation that no longer supports rosetta2
- mjevans 4y agoImplicit phrasing in the article suggests guests cannot enable the flag at all, as it's a CPU mode change. It might be important to bare metal OS writers though, hopefully those teams have already reverse engineered the method or are kindly answered by the manufacturer.
- dougall 4y agoI've only messed around in user-space, so I'm not sure how it's enabled. But if I were to guess, it might be bit 4 ("Enable APFLG") of ACTLR_EL1 ("(ARM standard-not-standard)"): https://github.com/AsahiLinux/docs/wiki/HW:ARM-System-Registers#actlr_el1-arm-standard-not-standard https://github.com/AsahiLinux/docs/wiki/HW:ARM-System-Regist...