> Do not doubt that the number of instructions will grow as large as is found in x86 and ARM, making a mockery of the "R". https://danluu.com/risc-definition/

> Do not doubt that the number of instructions will grow as large as is found in x86 and ARM, making a mockery of the "R". https://danluu.com/risc-definition/ https://danluu.com/risc-definition/ Number of instructions isn't what is "Reduced" in RISC, but rather the complexity of instructions: Single-width opcodes with very few addressing modes, such that pipelining is easy and taking exceptions is not as painful as it is when your opcodes have lots of ALU state, like with indirect addressing and opcodes that mix addressing modes with their own ALU operations. RISC is also somewhat nebulous, with some ISAs being "more RISC" (RISCier?) than others, and some RISC ideas (architectural delay slots, integer multiplication and divide opcodes requiring their own registers) eventually getting dropped entirely as chip technology moves on. > It is not a mistake to optimize an ISA for use in undergraduate courses, but probably is one to use identically the same ISA industrially. I don't know that a good ISA needs to be optimized for undergraduate courses to be used in them: MIPS is famously used in H&P and it has quite a following to this day, just not on the desktop or in servers. Was RISC-V optimized for use as a "model organism" like that?