4 ms·
When you see RISC replace it in your head with "load/store architecture". Like when you look at the SIMD implementations on x86 "CISC" machines they're all loa
by Veliladon 4y ago
When you see RISC replace it in your head with "load/store architecture".
Like when you look at the SIMD implementations on x86 "CISC" machines they're all load/store based instead of register/memory based like on the scalar and x87 implementations.
This is what people mean when they say RISC has won.
- notacoward 4y agoThe practical definition that came through from reading Computer Architecture: A Quantitative Approach by the two people who did most to make RISC happen (Hennessy at Stanford and Patterson at Berkeley) had to do with this formula. work/second = work/instruction * instructions/cycle * cycles/second The "reduction" in RISC was in work (and complexity) per instruction, enabling even greater gains in the other two factors. I'm well aware that this isn't the official definition, but IMO it's the perspective that has held up best through all the intervening years. Load/store is certainly part of that. So are orthogonal instruction and register sets, exposed pipelines, software TLBs, etc. We've gotten away from some of those things nowadays, but in the early days they were necessary to drive performance despite lower work per instruction.
- Veliladon 4y ago> exposed pipelines Oh boy. Good old branch delay slots on the earlier MIPS architectures.
- notacoward 4y agoBranch and load delays on the MC88K. I was working at Encore then, doing things like writing exception handlers and optimizing bcopy/memcpy. I actually enjoyed the puzzle-like aspect of it, but I totally got why others weren't into it.