5 ms·

>Do not doubt that the number of instructions will grow as large as is found in x86 and ARM x86 has at least ~1,000 instructions,[0][1] maybe more depending on

>Do not doubt that the number of instructions will grow as large as is found in x86 and ARM x86 has at least ~1,000 instructions,[0][1] maybe more depending on how you count. I can't believe RISC-V will approach that number. I couldn't easily find how many instructions arm64 has. But you may be right about RISC-6, only I think any "RISC-6" will just be RISC-V with less useful instructions depreciated [0]https://www.unomaha.edu/college-of-information-science-and-technology/research-labs/_files/enumerating-x86-64-instructions.pdf https://www.unomaha.edu/college-of-information-science-and-t... [1]https://fgiesen.wordpress.com/2016/08/25/how-many-x86-instructions-are-there/ https://fgiesen.wordpress.com/2016/08/25/how-many-x86-instru...

cwzwarich 4y ago
Number of distinct mnemonics doesn't really determine ISA complexity. As an extreme example, how many AArch64/RISC-V instructions are there corresponding to an x86 MOV?
- deleted 4y ago
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sparkie 4y ago
If you exclude AVX-512, the number is probably less than half that. And since Intel locked AVX-512 out of alder-lake processors, if you want a consume grade processor which supports it you would buy a Zen4 from AMD.
- Vt71fcAqt7 4y ago
  >If you exclude AVX-512, the number is probably less than half that. This paper seems to say there are thousands, am I reading it wrong? >There are two primary barriers to producing a formal specification of x86-64. First, the instruction set is huge: x86-64 contains 981 unique mnemonics and a total of 3,684 instruction variants.[0] [0]https://dl.acm.org/doi/10.1145/29809 https://dl.acm.org/doi/10.1145/29809
  - sparkie 4y ago
    AVX-512 is huge. See https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#techs=AVX_512 https://www.intel.com/content/www/us/en/docs/intrinsics-guid...
hajile 4y ago
That's 1k instructions ONLY in their most RISC-like form. It also generally excludes stuff like MOV effectively translating into countless instructions when you start looking at all it's variants based on source/destination type, data types, concatenated instructions tacked on, etc (MOV alone is technically Turing complete[0]). All that stuff is spelled out in the instruction and while it may have the same mnemonic, the actual binary output is different. In these terms, the actual number of instructions is likely in at least the tens of thousands. In comparison, RISC-V splits off loads and stores into separate instructions. It further splits off each size of load/store into even more instructions. Start clumping all of this stuff together and RISC-V instruction count would also plummet. [0] https://stackoverflow.com/questions/61048788/why-is-mov-turing-complete https://stackoverflow.com/questions/61048788/why-is-mov-turi...

cwzwarich 4y ago

Number of distinct mnemonics doesn't really determine ISA complexity. As an extreme example, how many AArch64/RISC-V instructions are there corresponding to an x86 MOV?

deleted 4y ago
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sparkie 4y ago

If you exclude AVX-512, the number is probably less than half that. And since Intel locked AVX-512 out of alder-lake processors, if you want a consume grade processor which supports it you would buy a Zen4 from AMD.

Vt71fcAqt7 4y ago
>If you exclude AVX-512, the number is probably less than half that. This paper seems to say there are thousands, am I reading it wrong? >There are two primary barriers to producing a formal specification of x86-64. First, the instruction set is huge: x86-64 contains 981 unique mnemonics and a total of 3,684 instruction variants.[0] [0]https://dl.acm.org/doi/10.1145/29809 https://dl.acm.org/doi/10.1145/29809
- sparkie 4y ago
  AVX-512 is huge. See https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#techs=AVX_512 https://www.intel.com/content/www/us/en/docs/intrinsics-guid...

hajile 4y ago

That's 1k instructions ONLY in their most RISC-like form. It also generally excludes stuff like MOV effectively translating into countless instructions when you start looking at all it's variants based on source/destination type, data types, concatenated instructions tacked on, etc (MOV alone is technically Turing complete[0]). All that stuff is spelled out in the instruction and while it may have the same mnemonic, the actual binary output is different. In these terms, the actual number of instructions is likely in at least the tens of thousands. In comparison, RISC-V splits off loads and stores into separate instructions. It further splits off each size of load/store into even more instructions. Start clumping all of this stuff together and RISC-V instruction count would also plummet. [0] https://stackoverflow.com/questions/61048788/why-is-mov-turing-complete https://stackoverflow.com/questions/61048788/why-is-mov-turi...