4 ms·

Judging from the number of instructions in all its necessary extensions, RISC-V is RISC in name only. ARM ("Acorn RISC Machine") instructions are as absurdly ma

Judging from the number of instructions in all its necessary extensions, RISC-V is RISC in name only. ARM ("Acorn RISC Machine") instructions are as absurdly many as x86's, which does not even pretend to be RISC. So it is silly to say RISC has won.

Veliladon 4y ago
When you see RISC replace it in your head with "load/store architecture". Like when you look at the SIMD implementations on x86 "CISC" machines they're all load/store based instead of register/memory based like on the scalar and x87 implementations. This is what people mean when they say RISC has won.
- notacoward 4y ago
  The practical definition that came through from reading Computer Architecture: A Quantitative Approach by the two people who did most to make RISC happen (Hennessy at Stanford and Patterson at Berkeley) had to do with this formula. work/second = work/instruction * instructions/cycle * cycles/second The "reduction" in RISC was in work (and complexity) per instruction, enabling even greater gains in the other two factors. I'm well aware that this isn't the official definition, but IMO it's the perspective that has held up best through all the intervening years. Load/store is certainly part of that. So are orthogonal instruction and register sets, exposed pipelines, software TLBs, etc. We've gotten away from some of those things nowadays, but in the early days they were necessary to drive performance despite lower work per instruction.
  - Veliladon 4y ago
    > exposed pipelines Oh boy. Good old branch delay slots on the earlier MIPS architectures.
    - notacoward 4y ago
      Branch and load delays on the MC88K. I was working at Encore then, doing things like writing exception handlers and optimizing bcopy/memcpy. I actually enjoyed the puzzle-like aspect of it, but I totally got why others weren't into it.
Vt71fcAqt7 4y ago
>ARM ("Acorn RISC Machine") instructions are as absurdly many as x86's Can you give the number of x86_64, ARM64 and RISC-V instructions? I didn't think ARM64 had 1000s of instructions.
an-unknown 4y ago
RISC has nothing to do with instruction counts. Think of it as a "set of reduced instructions", not a "reduced set of instructions". It's the fact that every instruction only does something "simple" which you can directly implement in hardware that matters here. In case it's still not obvious: PowerPC is obviously a RISC ISA, but it has just as many instructions as some CISC ISAs out there. Meanwhile PDP-8 has 8 instructions, but it's clearly a CISC ISA.
- sparkie 4y ago
  I think "do something simple" is going to get phased out and replaced by "do something useful" over time. Consider if you want to load a 64-bit immediate into a register under the current RISC-V spec. Takes so many instructions that it's easier to just load a constant from memory, despite memory access being much slower. lui r1, 0x01234 lui r2, 0x89ABC addi r1, 0x567 addi r2, 0xDEF shl r1, 32 or r1, r2 24-bytes, 6 instruction cycles and 2 registers. In x86_64: movabs rax, 0x0123456789ABCDEF 11-bytes, 1 instruction cycle, 1 register.
  - xpuente 4y ago
    How many uOps is that instruction in x86_64? Note that while the performance effect of L1I cache misses is negligible, the complex x86-64 decoder may not be. Some SPECpu2017 have front-end problems due to the x86-64 decoder.
    - colejohnson66 4y ago
      `MOV Rq, Iq` takes one uop with a throughput of up to four(!) per cycle on some ISAs: https://uops.info/html-instr/MOV_R64_I64.html https://uops.info/html-instr/MOV_R64_I64.html
      - deleted 4y ago
        [deleted]
  - zozbot234 4y ago

Veliladon 4y ago

When you see RISC replace it in your head with "load/store architecture". Like when you look at the SIMD implementations on x86 "CISC" machines they're all load/store based instead of register/memory based like on the scalar and x87 implementations. This is what people mean when they say RISC has won.

notacoward 4y ago
The practical definition that came through from reading Computer Architecture: A Quantitative Approach by the two people who did most to make RISC happen (Hennessy at Stanford and Patterson at Berkeley) had to do with this formula. work/second = work/instruction * instructions/cycle * cycles/second The "reduction" in RISC was in work (and complexity) per instruction, enabling even greater gains in the other two factors. I'm well aware that this isn't the official definition, but IMO it's the perspective that has held up best through all the intervening years. Load/store is certainly part of that. So are orthogonal instruction and register sets, exposed pipelines, software TLBs, etc. We've gotten away from some of those things nowadays, but in the early days they were necessary to drive performance despite lower work per instruction.
- Veliladon 4y ago
  > exposed pipelines Oh boy. Good old branch delay slots on the earlier MIPS architectures.
  - notacoward 4y ago
    Branch and load delays on the MC88K. I was working at Encore then, doing things like writing exception handlers and optimizing bcopy/memcpy. I actually enjoyed the puzzle-like aspect of it, but I totally got why others weren't into it.

Vt71fcAqt7 4y ago

>ARM ("Acorn RISC Machine") instructions are as absurdly many as x86's Can you give the number of x86_64, ARM64 and RISC-V instructions? I didn't think ARM64 had 1000s of instructions.

an-unknown 4y ago

RISC has nothing to do with instruction counts. Think of it as a "set of reduced instructions", not a "reduced set of instructions". It's the fact that every instruction only does something "simple" which you can directly implement in hardware that matters here. In case it's still not obvious: PowerPC is obviously a RISC ISA, but it has just as many instructions as some CISC ISAs out there. Meanwhile PDP-8 has 8 instructions, but it's clearly a CISC ISA.

sparkie 4y ago
I think "do something simple" is going to get phased out and replaced by "do something useful" over time. Consider if you want to load a 64-bit immediate into a register under the current RISC-V spec. Takes so many instructions that it's easier to just load a constant from memory, despite memory access being much slower. lui r1, 0x01234 lui r2, 0x89ABC addi r1, 0x567 addi r2, 0xDEF shl r1, 32 or r1, r2 24-bytes, 6 instruction cycles and 2 registers. In x86_64: movabs rax, 0x0123456789ABCDEF 11-bytes, 1 instruction cycle, 1 register.
- xpuente 4y ago
  How many uOps is that instruction in x86_64? Note that while the performance effect of L1I cache misses is negligible, the complex x86-64 decoder may not be. Some SPECpu2017 have front-end problems due to the x86-64 decoder.
  - colejohnson66 4y ago
    `MOV Rq, Iq` takes one uop with a throughput of up to four(!) per cycle on some ISAs: https://uops.info/html-instr/MOV_R64_I64.html https://uops.info/html-instr/MOV_R64_I64.html
    - deleted 4y ago
      [deleted]
- zozbot234 4y ago