5 ms·

RV is an open-ended collection of ISAs. Do not doubt that the number of instructions will grow as large as is found in x86 and ARM, making a mockery of the "R".

RV is an open-ended collection of ISAs. Do not doubt that the number of instructions will grow as large as is found in x86 and ARM, making a mockery of the "R". I am ready for the successor, Risc-6, already. It can retain most details of RISC-V while fixing its more glaring deficiencies. It is not a mistake to optimize an ISA for use in undergraduate courses, but probably is one to use identically the same ISA industrially. I don't know if the worst deficiency is the need to fuse up to 5 consecutive instructions to get useful operations per clock cycle to a competitive level. While fixing serious problems, numerous smaller incidentals could be patched, such as having chosen the architectural representation of "true" to be 1 instead of -1.

Vt71fcAqt7 4y ago
>Do not doubt that the number of instructions will grow as large as is found in x86 and ARM x86 has at least ~1,000 instructions,[0][1] maybe more depending on how you count. I can't believe RISC-V will approach that number. I couldn't easily find how many instructions arm64 has. But you may be right about RISC-6, only I think any "RISC-6" will just be RISC-V with less useful instructions depreciated [0]https://www.unomaha.edu/college-of-information-science-and-technology/research-labs/_files/enumerating-x86-64-instructions.pdf https://www.unomaha.edu/college-of-information-science-and-t... [1]https://fgiesen.wordpress.com/2016/08/25/how-many-x86-instructions-are-there/ https://fgiesen.wordpress.com/2016/08/25/how-many-x86-instru...
- cwzwarich 4y ago
  Number of distinct mnemonics doesn't really determine ISA complexity. As an extreme example, how many AArch64/RISC-V instructions are there corresponding to an x86 MOV?
  - deleted 4y ago
    [deleted]
- sparkie 4y ago
  If you exclude AVX-512, the number is probably less than half that. And since Intel locked AVX-512 out of alder-lake processors, if you want a consume grade processor which supports it you would buy a Zen4 from AMD.
  - Vt71fcAqt7 4y ago
    >If you exclude AVX-512, the number is probably less than half that. This paper seems to say there are thousands, am I reading it wrong? >There are two primary barriers to producing a formal specification of x86-64. First, the instruction set is huge: x86-64 contains 981 unique mnemonics and a total of 3,684 instruction variants.[0] [0]https://dl.acm.org/doi/10.1145/29809 https://dl.acm.org/doi/10.1145/29809
    - sparkie 4y ago
      AVX-512 is huge. See https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#techs=AVX_512 https://www.intel.com/content/www/us/en/docs/intrinsics-guid...
- hajile 4y ago
  That's 1k instructions ONLY in their most RISC-like form. It also generally excludes stuff like MOV effectively translating into countless instructions when you start looking at all it's variants based on source/destination type, data types, concatenated instructions tacked on, etc (MOV alone is technically Turing complete[0]). All that stuff is spelled out in the instruction and while it may have the same mnemonic, the actual binary output is different. In these terms, the actual number of instructions is likely in at least the tens of thousands. In comparison, RISC-V splits off loads and stores into separate instructions. It further splits off each size of load/store into even more instructions. Start clumping all of this stuff together and RISC-V instruction count would also plummet. [0] https://stackoverflow.com/questions/61048788/why-is-mov-turing-complete https://stackoverflow.com/questions/61048788/why-is-mov-turi...
sparkie 4y ago
The number of instructions is already becoming quite large if you consider the V and P extensions. Here's the vector instructions: https://github.com/riscv/riscv-v-spec/blob/master/inst-table.adoc https://github.com/riscv/riscv-v-spec/blob/master/inst-table... The set of RISC-V features that each CPU supports is going to be so widely varied that you will need dozens of compiler switches to make full use any processor, and since most software will be compiled for the lowest-common-denominator, some capabilities will go largely unused. This is already the case with x86 with AVX-512, the full capabilities are only leveraged in specific workloads. Either that or developers are going to rethink the way they distribute software. No longer as compiled binaries, but as an IR which is then compiled on each processor, since the best way to learn what features are supported by any CPU is to query them on it.
- pjmlp 4y ago
  That is how mainframes and micro-computers have been doing since forever. I guess it is time for another great idea for VCs, I know, let's create a WASM runtime for RISC-V.
- addaon 4y ago
  Or OS authors are going to have to rethink how they handle illegal instruction exceptions, by patching the calling program to call into an emulated version when running on hardware that lacks support; this would allow program authors to choose whether to favor the least common denominator (and give up performance on more capable processors) or to target best possible performance (but take a hit on more limited machines). An ABI that reserves a few registers for this sort of emulation, or a couple or reserved architectural registers, could help a lot.
  - pclmulqdq 4y ago
    Nobody is going to be patching calling programs like this. There may be OS emulation in machine mode (saving and restoring the register file) to pretend to be a "generic" RISC-V.
    - 4y ago
msla 4y ago
> Do not doubt that the number of instructions will grow as large as is found in x86 and ARM, making a mockery of the "R". https://danluu.com/risc-definition/ https://danluu.com/risc-definition/ Number of instructions isn't what is "Reduced" in RISC, but rather the complexity of instructions: Single-width opcodes with very few addressing modes, such that pipelining is easy and taking exceptions is not as painful as it is when your opcodes have lots of ALU state, like with indirect addressing and opcodes that mix addressing modes with their own ALU operations. RISC is also somewhat nebulous, with some ISAs being "more RISC" (RISCier?) than others, and some RISC ideas (architectural delay slots, integer multiplication and divide opcodes requiring their own registers) eventually getting dropped entirely as chip technology moves on. > It is not a mistake to optimize an ISA for use in undergraduate courses, but probably is one to use identically the same ISA industrially. I don't know that a good ISA needs to be optimized for undergraduate courses to be used in them: MIPS is famously used in H&P and it has quite a following to this day, just not on the desktop or in servers. Was RISC-V optimized for use as a "model organism" like that?
- pencilguin 4y ago
  Let us not forget SPARC's register windows. I don't know if you could say RISC-V was optimized, as such, for undergraduate courses, but historically that was its design target. That said, there was a lot more attention to extensibility via regularized instruction set extensions than the undergraduate target demanded. RISC-V's permanently-zero register is akin to other RISCs' special multiplication registers.
hoosieree 4y ago
I always pronounce RISC-V in my head as "RISC VEE". Even "RISC OR" is easier for me. If they call the successor RISC-VI then I'll probably mentally autocorrect it to "RISC-VIM" anyway, it's a lost cause.
- pencilguin 4y ago
  I pronounce it "riskive", myself. Had there been a RISC-IV it would have been pronounced the same, so it is lucky there wasn't one.
glhaynes 4y ago
While fixing serious problems, numerous smaller incidentals could be patched, such as having chosen the architectural representation of "true" to be 1 instead of -1. What issues does that cause? Finding it difficult to web search for…
- a1369209993 4y ago
  The only one I recall of the top of my head is that it makes `first & bool | second & ~bool` faster, since you don't need a `dec r0` instruction to turn {0,1} into a bitmask. Anyone else have a better guess?
  - pencilguin 4y ago
    "that & bool", yielding either zero or "that", is common enough, by itself, to matter.
    - a1369209993 4y ago
      Huh, good point, actually; I'd overlooked that, eg in `sum += filter[i] & elem[i]`.

Vt71fcAqt7 4y ago

>Do not doubt that the number of instructions will grow as large as is found in x86 and ARM x86 has at least ~1,000 instructions,[0][1] maybe more depending on how you count. I can't believe RISC-V will approach that number. I couldn't easily find how many instructions arm64 has. But you may be right about RISC-6, only I think any "RISC-6" will just be RISC-V with less useful instructions depreciated [0]https://www.unomaha.edu/college-of-information-science-and-technology/research-labs/_files/enumerating-x86-64-instructions.pdf https://www.unomaha.edu/college-of-information-science-and-t... [1]https://fgiesen.wordpress.com/2016/08/25/how-many-x86-instructions-are-there/ https://fgiesen.wordpress.com/2016/08/25/how-many-x86-instru...

cwzwarich 4y ago
Number of distinct mnemonics doesn't really determine ISA complexity. As an extreme example, how many AArch64/RISC-V instructions are there corresponding to an x86 MOV?
- deleted 4y ago
  [deleted]
sparkie 4y ago
If you exclude AVX-512, the number is probably less than half that. And since Intel locked AVX-512 out of alder-lake processors, if you want a consume grade processor which supports it you would buy a Zen4 from AMD.
- Vt71fcAqt7 4y ago
  >If you exclude AVX-512, the number is probably less than half that. This paper seems to say there are thousands, am I reading it wrong? >There are two primary barriers to producing a formal specification of x86-64. First, the instruction set is huge: x86-64 contains 981 unique mnemonics and a total of 3,684 instruction variants.[0] [0]https://dl.acm.org/doi/10.1145/29809 https://dl.acm.org/doi/10.1145/29809
  - sparkie 4y ago
    AVX-512 is huge. See https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#techs=AVX_512 https://www.intel.com/content/www/us/en/docs/intrinsics-guid...
hajile 4y ago
That's 1k instructions ONLY in their most RISC-like form. It also generally excludes stuff like MOV effectively translating into countless instructions when you start looking at all it's variants based on source/destination type, data types, concatenated instructions tacked on, etc (MOV alone is technically Turing complete[0]). All that stuff is spelled out in the instruction and while it may have the same mnemonic, the actual binary output is different. In these terms, the actual number of instructions is likely in at least the tens of thousands. In comparison, RISC-V splits off loads and stores into separate instructions. It further splits off each size of load/store into even more instructions. Start clumping all of this stuff together and RISC-V instruction count would also plummet. [0] https://stackoverflow.com/questions/61048788/why-is-mov-turing-complete https://stackoverflow.com/questions/61048788/why-is-mov-turi...

sparkie 4y ago

The number of instructions is already becoming quite large if you consider the V and P extensions. Here's the vector instructions: https://github.com/riscv/riscv-v-spec/blob/master/inst-table.adoc https://github.com/riscv/riscv-v-spec/blob/master/inst-table... The set of RISC-V features that each CPU supports is going to be so widely varied that you will need dozens of compiler switches to make full use any processor, and since most software will be compiled for the lowest-common-denominator, some capabilities will go largely unused. This is already the case with x86 with AVX-512, the full capabilities are only leveraged in specific workloads. Either that or developers are going to rethink the way they distribute software. No longer as compiled binaries, but as an IR which is then compiled on each processor, since the best way to learn what features are supported by any CPU is to query them on it.

pjmlp 4y ago
That is how mainframes and micro-computers have been doing since forever. I guess it is time for another great idea for VCs, I know, let's create a WASM runtime for RISC-V.
addaon 4y ago
Or OS authors are going to have to rethink how they handle illegal instruction exceptions, by patching the calling program to call into an emulated version when running on hardware that lacks support; this would allow program authors to choose whether to favor the least common denominator (and give up performance on more capable processors) or to target best possible performance (but take a hit on more limited machines). An ABI that reserves a few registers for this sort of emulation, or a couple or reserved architectural registers, could help a lot.
- pclmulqdq 4y ago
  Nobody is going to be patching calling programs like this. There may be OS emulation in machine mode (saving and restoring the register file) to pretend to be a "generic" RISC-V.
  - 4y ago

msla 4y ago

> Do not doubt that the number of instructions will grow as large as is found in x86 and ARM, making a mockery of the "R". https://danluu.com/risc-definition/ https://danluu.com/risc-definition/ Number of instructions isn't what is "Reduced" in RISC, but rather the complexity of instructions: Single-width opcodes with very few addressing modes, such that pipelining is easy and taking exceptions is not as painful as it is when your opcodes have lots of ALU state, like with indirect addressing and opcodes that mix addressing modes with their own ALU operations. RISC is also somewhat nebulous, with some ISAs being "more RISC" (RISCier?) than others, and some RISC ideas (architectural delay slots, integer multiplication and divide opcodes requiring their own registers) eventually getting dropped entirely as chip technology moves on. > It is not a mistake to optimize an ISA for use in undergraduate courses, but probably is one to use identically the same ISA industrially. I don't know that a good ISA needs to be optimized for undergraduate courses to be used in them: MIPS is famously used in H&P and it has quite a following to this day, just not on the desktop or in servers. Was RISC-V optimized for use as a "model organism" like that?

pencilguin 4y ago
Let us not forget SPARC's register windows. I don't know if you could say RISC-V was optimized, as such, for undergraduate courses, but historically that was its design target. That said, there was a lot more attention to extensibility via regularized instruction set extensions than the undergraduate target demanded. RISC-V's permanently-zero register is akin to other RISCs' special multiplication registers.

hoosieree 4y ago

I always pronounce RISC-V in my head as "RISC VEE". Even "RISC OR" is easier for me. If they call the successor RISC-VI then I'll probably mentally autocorrect it to "RISC-VIM" anyway, it's a lost cause.

pencilguin 4y ago
I pronounce it "riskive", myself. Had there been a RISC-IV it would have been pronounced the same, so it is lucky there wasn't one.

glhaynes 4y ago

While fixing serious problems, numerous smaller incidentals could be patched, such as having chosen the architectural representation of "true" to be 1 instead of -1. What issues does that cause? Finding it difficult to web search for…

a1369209993 4y ago
The only one I recall of the top of my head is that it makes `first & bool | second & ~bool` faster, since you don't need a `dec r0` instruction to turn {0,1} into a bitmask. Anyone else have a better guess?
- pencilguin 4y ago
  "that & bool", yielding either zero or "that", is common enough, by itself, to matter.
  - a1369209993 4y ago
    Huh, good point, actually; I'd overlooked that, eg in `sum += filter[i] & elem[i]`.