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They get many mentions in early RISC-V rationale and even the spec itself. There were reasons not to use these architectures, even when/if open.
by snvzz 4y ago
They get many mentions in early RISC-V rationale and even the spec itself.
There were reasons not to use these architectures, even when/if open.
- chasil 4y agoMIPS and SPARC blew everybody out of the water at their introduction, but they sacrificed elements of the instruction set for immediate/generational performance gains. "RISC II proved to be much more successful in silicon and in testing outperformed almost all minicomputers on almost all tasks. For instance, performance ranged from 85% of VAX speed to 256% on a variety of loads. RISC II was also benched against the famous Motorola 68000, then considered to be the best commercial chip implementation, and outperformed it by 140% to 420%." https://en.wikipedia.org/wiki/Berkeley_RISC https://en.wikipedia.org/wiki/Berkeley_RISC [Not really much mention of MIPS performance relative to CISC minis.] https://en.wikipedia.org/wiki/Stanford_MIPS https://en.wikipedia.org/wiki/Stanford_MIPS https://en.wikipedia.org/wiki/R2000_microprocessor https://en.wikipedia.org/wiki/R2000_microprocessor