>but that would probably require a larger decoding stage. The evidence so far points to the opposite. Existing RISC-V µarch from e.g. Andes and SiFive offer p

>but that would probably require a larger decoding stage. The evidence so far points to the opposite. Existing RISC-V µarch from e.g. Andes and SiFive offer performance that matches or beats the ARM cores they're positioned against, with considerably lower power and significantly smaller area. And they do already have an answer for most of ARM's own lineup, covering from the smallest cores to the higher performing ones, solely excluding the very newest, highest performance targeting cores, where the gap is already under 2 years.