3 ms·

Sounds like a wonderful college experience. SPARCs are nice... I was a little before that, our assembly language course was 68000, which was a nice step up from

Sounds like a wonderful college experience. SPARCs are nice... I was a little before that, our assembly language course was 68000, which was a nice step up from 6502 I was familiar with. But I do love RISCs. I am curious what were the main things you liked about SPARC and disliked about ARM?

snvzz 4y ago
Mine used MIPS. It sure varies depending on university. These days, RISC-V seems to be quickly gaining terrain in academia.
- chasil 4y ago
  Admiration for SPARC and MIPS is not universal, and there were interesting warts on these early designs that did not age well. https://www.jwhitham.org//2016/02/risc-instruction-sets-i-have-known-and.html https://www.jwhitham.org//2016/02/risc-instruction-sets-i-ha... https://news.ycombinator.com/item?id=11607119 https://news.ycombinator.com/item?id=11607119
  - snvzz 4y ago
    They get many mentions in early RISC-V rationale and even the spec itself. There were reasons not to use these architectures, even when/if open.
    - chasil 4y ago
      MIPS and SPARC blew everybody out of the water at their introduction, but they sacrificed elements of the instruction set for immediate/generational performance gains. "RISC II proved to be much more successful in silicon and in testing outperformed almost all minicomputers on almost all tasks. For instance, performance ranged from 85% of VAX speed to 256% on a variety of loads. RISC II was also benched against the famous Motorola 68000, then considered to be the best commercial chip implementation, and outperformed it by 140% to 420%." https://en.wikipedia.org/wiki/Berkeley_RISC https://en.wikipedia.org/wiki/Berkeley_RISC [Not really much mention of MIPS performance relative to CISC minis.] https://en.wikipedia.org/wiki/Stanford_MIPS https://en.wikipedia.org/wiki/Stanford_MIPS https://en.wikipedia.org/wiki/R2000_microprocessor https://en.wikipedia.org/wiki/R2000_microprocessor
  - torstenvl 4y ago
    Predictable pipelining and delay slots were easy to adjust to and understand, and I love the idea of a rotating register file with zero-copy call stack, even though it's impractical today. The author claims memorizing how the registers overwrite one another is complicated, but I don't think so at all. G registers are global (with g0 always being 0). L registers are local. I (input) registers are the interface with the caller, O (output registers) are the interface with the callee, and the overlapping register window just moves so that O registers are I registers in the called function. Elegant. Also the author goes on to praise x86, which is absolutely fucking bananas if you care about not having to rote memorize register names. I'm calling a function with four word-sized arguments. In SPARC they go in %o0, %o1, %o2, and %o3. Where do they go in x86?
    - ZirconiumX 4y ago
      DIre SIlicon DeXtrously Concatenates 8 and 9 (for SysV). Jubilee[1] came up with that and it's a useful mnemonic. [1]: https://twitter.com/workingjubilee https://twitter.com/workingjubilee

snvzz 4y ago

Mine used MIPS. It sure varies depending on university. These days, RISC-V seems to be quickly gaining terrain in academia.

chasil 4y ago
Admiration for SPARC and MIPS is not universal, and there were interesting warts on these early designs that did not age well. https://www.jwhitham.org//2016/02/risc-instruction-sets-i-have-known-and.html https://www.jwhitham.org//2016/02/risc-instruction-sets-i-ha... https://news.ycombinator.com/item?id=11607119 https://news.ycombinator.com/item?id=11607119
- snvzz 4y ago
  They get many mentions in early RISC-V rationale and even the spec itself. There were reasons not to use these architectures, even when/if open.
  - chasil 4y ago
    MIPS and SPARC blew everybody out of the water at their introduction, but they sacrificed elements of the instruction set for immediate/generational performance gains. "RISC II proved to be much more successful in silicon and in testing outperformed almost all minicomputers on almost all tasks. For instance, performance ranged from 85% of VAX speed to 256% on a variety of loads. RISC II was also benched against the famous Motorola 68000, then considered to be the best commercial chip implementation, and outperformed it by 140% to 420%." https://en.wikipedia.org/wiki/Berkeley_RISC https://en.wikipedia.org/wiki/Berkeley_RISC [Not really much mention of MIPS performance relative to CISC minis.] https://en.wikipedia.org/wiki/Stanford_MIPS https://en.wikipedia.org/wiki/Stanford_MIPS https://en.wikipedia.org/wiki/R2000_microprocessor https://en.wikipedia.org/wiki/R2000_microprocessor
- torstenvl 4y ago
  Predictable pipelining and delay slots were easy to adjust to and understand, and I love the idea of a rotating register file with zero-copy call stack, even though it's impractical today. The author claims memorizing how the registers overwrite one another is complicated, but I don't think so at all. G registers are global (with g0 always being 0). L registers are local. I (input) registers are the interface with the caller, O (output registers) are the interface with the callee, and the overlapping register window just moves so that O registers are I registers in the called function. Elegant. Also the author goes on to praise x86, which is absolutely fucking bananas if you care about not having to rote memorize register names. I'm calling a function with four word-sized arguments. In SPARC they go in %o0, %o1, %o2, and %o3. Where do they go in x86?
  - ZirconiumX 4y ago
    DIre SIlicon DeXtrously Concatenates 8 and 9 (for SysV). Jubilee[1] came up with that and it's a useful mnemonic. [1]: https://twitter.com/workingjubilee https://twitter.com/workingjubilee