5 ms·
It's not immediately clear either way, but I'm guessing this is based on composable / software defined infrastructure components, like e.g. CXL memory.
by rch 4y ago
It's not immediately clear either way, but I'm guessing this is based on composable / software defined infrastructure components, like e.g. CXL memory.
- wmf 4y agoNo, because that stuff does not exist.
- dragontamer 4y agoIf its from IBM Telum processors, this is the weird processor where a processor's L2 cache serves as the L3 and L4 caches of other processors. The processors network with each other, notice when they're not using all of their caches, and shares that cache with things far away (ie: in side the box, or even outside the box). This way, IBM can overprovision L2 cache and "not worry" about it going unused. Remote L2 cache is slower than local L2 cache, but its still SRAM and should still be faster than DRAM to access.
- rch 4y agoMakes sense. I'd seen Telum in the description, but I guess I was inferring too much from a note about 'changing workloads'.
- datameta 4y agoThere is even L4, which is accessing the L3 of another drawer - which in some cases is faster than accessing DRAM in the same drawer!
- webmobdev 4y agoSharing the cache is innovative. What architecture do these processors run - powerpc?
- wmf 4y agoz/Architecture
- exikyut 4y agoIs L2 faster than maximum PCI-e bandwidth, and would it be interesting to bolt some MMIO'd SRAM to an x86 box?