The general principle is that RISC style instruction sets are typically fixed length and with only a couple different subformats. Like the prototypical RISC des

The general principle is that RISC style instruction sets are typically fixed length and with only a couple different subformats. Like the prototypical RISC design has one format with an opcode and 3 register fields, and then a second with an opcode and an immediate field. This simplicity and regularity makes the fastest possible decoding hardware much more simple and efficient compared to something like x86 that has a simply dumbfounding number of possible variable length formats. The basic bet of RISC was that larger instruction encodings would be worth it due to the micro architectural advantages they enabled. This more or less was proven out, though the distinction is less distinct today with x86 decoding into uOps and recent ARM standards being quite complex beasts.