An underlying problem here is that we have come to favor computers that scales out the Von Neumann architecture with more cache coherent cores and more memory.

An underlying problem here is that we have come to favor computers that scales out the Von Neumann architecture with more cache coherent cores and more memory. If we take the path of hardware that implements smaller Von Neumann scales, and rather partitions smaller sets of cores and memory into actors that communicate with memssages we would get lower memory latency and less penalty from random access patterns.