I posted this on the YouTube comments as well. I’m pretty sure there is minor bug in how he uses 7 cpu cycles to try to read from the middle of each pulse. It s

I posted this on the YouTube comments as well. I’m pretty sure there is minor bug in how he uses 7 cpu cycles to try to read from the middle of each pulse. It should be about 50. He divided the 13 cycle wait in half but the reason he used 13 cycles originally is because the read logic was already using many cycles. In practice this doesn’t matter because the state transitions are stable enough with his particular device.