It's also an area where the costs are a lot less significant either: a cortex m4 and below often doesn't have a cache (at least for RAM: flash often has a cache

It's also an area where the costs are a lot less significant either: a cortex m4 and below often doesn't have a cache (at least for RAM: flash often has a cache and predictive lookup, but the perfomance difference is small enough that the cache can basically render executing code from flash as identical to RAM), and the RAM is about as fast as the processor, so random access and sequential access are pretty similar performance wise. (And with the speed of modern microcontroller cores the size of the data is rarely even an issue: most STM32s can iterate through their entire RAM in under a millisecond). That said, in my embedded work I still rarely find a linked list to be a useful data structure (but I know FreeRTOS, which I use a lot, uses them extremely heavily internally).