The last I heard was TSMC's mask count for 3nm chips is back at just under 100. EULV had brought it down but it's right up there again at the latest node. You r

The last I heard was TSMC's mask count for 3nm chips is back at just under 100. EULV had brought it down but it's right up there again at the latest node. You really need to avoid those all-layer re-spins!