I've been in the semiconductor industry for 25 years. Intel has tried to be a fab to external customers multiple times in the past. I can remember around 2002

I've been in the semiconductor industry for 25 years. Intel has tried to be a fab to external customers multiple times in the past. I can remember around 2002 and 2009. After a few years the effort dies out. I know a couple of companies that tried to get Intel to fab stuff and their orders get shoved aside when Intel needs the fab space for their own chips. The people who founded the company Open Silicon (physical design services) were kind of a spin off from Intel's design services group. They got frustrated when Intel wasn't serious about doing external chips. I know a couple of other 3rd party external IP companies that have designed IP for Intel in Intel's process. They all said the DRC rules were very restrictive. These blocks had a large amount of analog circuits where the layout is done by hand. In contrast I am in digital physical design where we use automated tools for most of it and follow DRC rules provided by the fab. When they went to check the DRC rules for their analog design they found techniques you could use at TSMC were not allowed by Intel. TSMC optimizes their process and rules so that 1,000 different companies can each make 1 million chips. If the yield is 80% then that's fine because in order to get the yield to 90% you would have to hire another 50 engineers and spend another 6 months of design time. Intel optimizes their process so that 1 company can make 5 chips 1 billion times each. They can throw another 100 engineers at it and get the yield to 90% because they are making so few different types of chips. EDIT: Regarding DRC rules: All fabs have DRC rules. These define things like metal layer 2 can't be thinner than X amount and if it is parallel to another segment of metal 2 for longer than 20 microns then the spacing needs to be increased. Vias on layer 13 are larger than on layer 12. The rule for minimum size and the spacing between a 4 x 3 grid of vias is different for via layer 13 vs 12. And so on TSMC has their mandatory DRC rules. They will not manufacture the chip for you if you don't meet all the rules or get waivers for special requests. Then they have their recommended rules. If you meet these the yield will be higher but many of them involve leaving even more space between wires. This increase your die area which increases cost. But the yield will be higher. So do you save money or lose money? We have people in our team to analyze this and decide that we will meet THESE recommended rules but not THOSE rules. TSMC also had suggested DRC rules. These would increase yield even more with the tradeoff of more design time spent to do it.