3 ms·

When the lines are smaller, you can place more transistors/functionality in the same area, which leads to higher performance. The power required decreases too.

by scns 4y ago

saberience 4y ago
Can you explain how the transistors are placed on the glass? Are they also "etched" by the EUV light?
- rusticpenn 4y ago
  They are etched and filled with different elements. So a traditional mosfet Transistor needs n, p and gate layers.
- elsjaako 4y ago
  They are put on there by putting chemicals on specificatic places. Because it's such a complex pattern, it's easiest to use a template and spray the chemicals on, the same way some artists apply spraypaint. The template is first printed on the glass. This is done by putting a light sensitive layer (photoresist) on the glass, and exposing some of it to light. When the light gets put on there the properties of the photoresist change so you can wash off the parts you don't want. Jl6 called this process "etching" (there may be additional steps that can also be described as etching, I don't know. Semiconductors are made with a lot of processes. This is the most well known process). Then you spray on the chemicals you want, and then you wash away the remaining photoresist so you can put the next layer on. This happens a lot of times for a modern chip.
- aastronaut 4y ago
  Additional to what has been posted already, the shape of the lines (which ultimately will result in transistors) is defined by manufactured patterns on quartz glass photomasks[1]. AFAIK a modern processor design has a stack of around 40-60 masks placed in sequence for the light to pass through. Producing these photomasks follows a similar manufacturing process from a lithography POV, except that electron-beams[2] are used instead of a light source. The mask manufacturing process requires its own specialized machines and Intel owns companies that produce those, eg. IMS Nanofabrication[3]. [1]: https://en.wikichip.org/wiki/mask https://en.wikichip.org/wiki/mask [2]: https://en.wikipedia.org/wiki/Electron-beam_lithography https://en.wikipedia.org/wiki/Electron-beam_lithography [3]: https://www.ims.co.at/en/ https://www.ims.co.at/en/
  - nsteel 4y ago
    The last I heard was TSMC's mask count for 3nm chips is back at just under 100. EULV had brought it down but it's right up there again at the latest node. You really need to avoid those all-layer re-spins!
- projektfu 4y ago
  I looked around at several ELI5-type sources and honestly the Wikipedia one is the best I came across. https://en.wikipedia.org/wiki/Wafer_fabrication https://en.wikipedia.org/wiki/Wafer_fabrication Here is ASML specifically, in a very slow slideshow format, representing our finest web technology. https://www.asml.com/en/technology/all-about-microchips/how-microchips-are-made https://www.asml.com/en/technology/all-about-microchips/how-...

When the lines are smaller, you can place more transistors/functionality in the same area, which leads to higher performance. The power required decreases too.

by scns 4y ago

When the lines are smaller, you can place more transistors/functionality in the same area, which leads to higher performance. The power required decreases too.

saberience 4y ago

Can you explain how the transistors are placed on the glass? Are they also "etched" by the EUV light?

rusticpenn 4y ago
They are etched and filled with different elements. So a traditional mosfet Transistor needs n, p and gate layers.
elsjaako 4y ago
They are put on there by putting chemicals on specificatic places. Because it's such a complex pattern, it's easiest to use a template and spray the chemicals on, the same way some artists apply spraypaint. The template is first printed on the glass. This is done by putting a light sensitive layer (photoresist) on the glass, and exposing some of it to light. When the light gets put on there the properties of the photoresist change so you can wash off the parts you don't want. Jl6 called this process "etching" (there may be additional steps that can also be described as etching, I don't know. Semiconductors are made with a lot of processes. This is the most well known process). Then you spray on the chemicals you want, and then you wash away the remaining photoresist so you can put the next layer on. This happens a lot of times for a modern chip.
aastronaut 4y ago
Additional to what has been posted already, the shape of the lines (which ultimately will result in transistors) is defined by manufactured patterns on quartz glass photomasks[1]. AFAIK a modern processor design has a stack of around 40-60 masks placed in sequence for the light to pass through. Producing these photomasks follows a similar manufacturing process from a lithography POV, except that electron-beams[2] are used instead of a light source. The mask manufacturing process requires its own specialized machines and Intel owns companies that produce those, eg. IMS Nanofabrication[3]. [1]: https://en.wikichip.org/wiki/mask https://en.wikichip.org/wiki/mask [2]: https://en.wikipedia.org/wiki/Electron-beam_lithography https://en.wikipedia.org/wiki/Electron-beam_lithography [3]: https://www.ims.co.at/en/ https://www.ims.co.at/en/
- nsteel 4y ago
  The last I heard was TSMC's mask count for 3nm chips is back at just under 100. EULV had brought it down but it's right up there again at the latest node. You really need to avoid those all-layer re-spins!
projektfu 4y ago
I looked around at several ELI5-type sources and honestly the Wikipedia one is the best I came across. https://en.wikipedia.org/wiki/Wafer_fabrication https://en.wikipedia.org/wiki/Wafer_fabrication Here is ASML specifically, in a very slow slideshow format, representing our finest web technology. https://www.asml.com/en/technology/all-about-microchips/how-microchips-are-made https://www.asml.com/en/technology/all-about-microchips/how-...