My MSEE thesis [0] innovated on classical CORDIC to modify it to reuse the three 18-bit adder/subtractors (one each for X-,Y-,Z-stages) into one Booth-recoded m

My MSEE thesis [0] innovated on classical CORDIC to modify it to reuse the three 18-bit adder/subtractors (one each for X-,Y-,Z-stages) into one Booth-recoded multipler retiring 6 bits/cycle. Hence it could complete an 18 x 18b multiplication in only three cycles (as opposed to 18 cycles or worse (+overheads) for classical CORDIC). Pretty neat, for almost zero extra gatecount (only a few muxes and control logic). (The motivation was that CORDIC with Walther's 1971 improvements performs great for trigonometric/hyperbolic/arc-functions, Euclidean distance, sqrt and also allows (bit-serial) division and multiplication - but still slow compared to array multipliers. This stuff was used in 1970s multifunction calculators (when area.) Since I decided to not do a PhD or do followup publications, my work proved the concept worked, then pretty much vanished into the conf literature. The concept is straightforward; if anyone out there wants to synthesize it on a Xilinx or similar, or do a soft-macro (Verilog/VHDL), and get some performance numbers, drop me a line. Also, Timmerman, Hahn, Hosticka did some good innovation in the 1990s on scaling, pipelining and latency. [1] But for most use-cases, you don't pipeline unless you really need to trade higher throughput off against minimal gatecount/silicon area and latency. And in the 1990s, there was interest in CORDIC for matrix triangularization and SVD. [0]: "Hybrid multiplier/CORDIC unit", IEEE ICASSP-99 https://ieeexplore.ieee.org/abstract/document/758297 https://ieeexplore.ieee.org/abstract/document/758297 [1]: https://scholar.google.com/scholar?hl=en&as_sdt=0%2C5&q=cordic+timmerman+hahn+hosticka&btnG= https://scholar.google.com/scholar?hl=en&as_sdt=0%2C5&q=cord...