4 ms·
Ok, so you are talking about rowhammer. Let me try to put this in my own words. https://people.freebsd.org/~lstewart/articles/cpumemory.pdf https://people.free
by majke 4y ago
Ok, so you are talking about rowhammer. Let me try to put this in my own words.
https://people.freebsd.org/~lstewart/articles/cpumemory.pdf https://people.freebsd.org/~lstewart/articles/cpumemory.pdf
DRAM is using hardware technology that is hard. Each dram bit can be addressed by ranks, banks, chips rows and columns. Depending on stuff, you typically read/load a whole cache line from DRAM. This is nice and easy. However, AFAIU there is delay needed in the chip after reading bytes. This means a read to subsequent cache line would be slow. Therefore, there is a strong reason to lay out subsequent data far away, ideally on different chips.
So you can read cache line #0 that can be on some physical chip #A and if you read line #1 it should not be on chip #A but ideally on a "random" other physical die.
This mapping, of "physical memory address" into actually where the data is on the DDRAM, is very much a hash function. This is usually done by the CPU manufacturer I guess. See the reversing of sandy bridge algo:
https://lackingrhoticity.blogspot.com/2015/04/l3-cache-mapping-on-sandy-bridge-cpus.html https://lackingrhoticity.blogspot.com/2015/04/l3-cache-mappi...
Rowhammer is an attack, where the attacker targets a single physical chip of DRAM and cause its misbehaviour due to keeping it active in unusal patterns. RowHammer is basically about reversing that hashing and exploiting the shortcuts dram manufacturers took when producing the chips.
https://blog.cloudflare.com/every-7-8us-your-computers-memory-has-a-hiccup/ https://blog.cloudflare.com/every-7-8us-your-computers-memor...
But this is about DRAM. I don't know how it works in Cache, but I don't think there is a special hashing algo. It just uses middle bits to address the cache line, as the parent article says.
- remram 4y agoThis is very interesting but doesn't really seem related to the comment you replied to?
- oso2k 4y agoIt is related because a naïve program will access a device (CPU registers, instruction pipelines, indirect cache access, RAM, disk, optical disk) in a linear fashion. RAM no longer has linear or near linear access. Disk drives of all types dealt with rotation speed, spindle head speed, etc. For a long time, disk specs were recorded in linear/sequential access time, full seek access time, and average random access time until sequential access time became less than 1ms and OSes/disk cache programs made average random access time the only latency worth caring about. In summary, most storage devices have hierarchical performance and it’s worth caring about how to optimize for that.