3 ms·
Under the hood, this hashing has existed for a long time, certainly since Haswell at Intel. However, Intel designed it to make sequential access still mostly s
by pclmulqdq 4y ago
Under the hood, this hashing has existed for a long time, certainly since Haswell at Intel. However, Intel designed it to make sequential access still mostly sequential, and combined it with prefetch logic that is decent at detecting strided access if you poke it the right way.
Also, main memory has a different hash than L3 cache does, and this hash is designed for sequential access.
- anonymoushn 4y agoCan I read more about this somewhere? On Haswell I've observed a 5% speedup (for a whole program that mostly does a bunch of other work) from spacing a bunch of arrays that are typically all pretty small and all accessed consecutively all the way through to have their start positions differ by some amount of cache lines other than a power of 2. So it certainly seemed to me like I was working with a set-associative cache where power of 2 strides were pathological.