It seems the bottleneck nowadays is mainly memory latency/throughput and thermo, the latter one is especially problematic for mobile devices due to less space f

It seems the bottleneck nowadays is mainly memory latency/throughput and thermo, the latter one is especially problematic for mobile devices due to less space for cooling. For memory, it seems that although we have higher throughput with DDR5, the latency is still high and we can only compensate it with larger cache, e.g. AMD 3D cache. For larger chips, you will get longer wires and may not be able to do things in 1 cycle. Assume that thermo is not an issue, you can probably cram many cores into 1 tiny chip, but the bus will probably be overloaded with too much traffic and long wire length. I think eventually cache coherency will be so expensive that we will go back to message passing for multicore or requires source/destination node ID for memory ordering...