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I predicted a LONG time ago that once we reached the physical limits computers would get bigger. Starting out with chiplet designs and then moving on to dinner-

I predicted a LONG time ago that once we reached the physical limits computers would get bigger. Starting out with chiplet designs and then moving on to dinner-plate type systems such as Cerebras. Our computers will become larger in size, maybe the size of a fridge in a couple of decades. Power requirements too will increase. I'm still hoping some wondrous material will be invented which will allow us to shrink chips still further. But it's obvious there's a limit how far we can go. The theoretical limit is still way off, though. It's about several million times the speed of current CPU's.

N1H1L 4y ago
We will definitely move to wide bandgap semiconductors fast, where we can run much higher switch speeds (aka clock rates) without overheating
- UltraViolence 4y ago
  I once read an article in Popular Science in the early 80's about the invention of quantum transistors at Texas Instruments. Are those what you mention?
  - N1H1L 4y ago
    Not really. Our substrate today is silicon (really n-type silicon). We build a city on top of that substrate. Modern semiconductors have become way more heterogenous in recent years. Our gate insulators are not silicon dioxides anymore but high-k dielectrics such as hafnium oxide. And even interconnects now have different compositions, such as cobalt and copper. But the substrate is still holding us back, and one reason for that is creating high-quality single crystal wafers for silicon that are way more manageable. The solution for a long time has been to use direct bandgap semiconductors such as GaN, AlN, and so on. Silicon is an indirect bandgap semiconductor, meaning its conduction and valence bands are not aligned in momentum space. As a result, electrons hopping between these bands pay a thermal penalty. GaN and AlN don't have that problem, and we now have a plethora of crystals (especially complex oxides) that are all direct, and we have an entire library of bandgaps to choose from. The problem is that we cannot easily make wafers from these direct bandgap systems. At least yet to be on any commercial scale. Honestly, rather than flushing billions of dollars down the toilet for Zuck's vanity projects - we should have spent money to scale up Czochralski's growth[1] for a ton of crystal families. But, as we are reaching the limits for reticule sizes and we move to chiplet architectures, maybe smaller wafers will work too? [1] https://en.wikipedia.org/wiki/Czochralski_method https://en.wikipedia.org/wiki/Czochralski_method
m3kw9 4y ago
The compute size needed will likely move to cloud. What they need is lower wireless latency, deterministic speeds and reliability for that to happen.
pca006132 4y ago
It seems the bottleneck nowadays is mainly memory latency/throughput and thermo, the latter one is especially problematic for mobile devices due to less space for cooling. For memory, it seems that although we have higher throughput with DDR5, the latency is still high and we can only compensate it with larger cache, e.g. AMD 3D cache. For larger chips, you will get longer wires and may not be able to do things in 1 cycle. Assume that thermo is not an issue, you can probably cram many cores into 1 tiny chip, but the bus will probably be overloaded with too much traffic and long wire length. I think eventually cache coherency will be so expensive that we will go back to message passing for multicore or requires source/destination node ID for memory ordering...

N1H1L 4y ago

We will definitely move to wide bandgap semiconductors fast, where we can run much higher switch speeds (aka clock rates) without overheating

UltraViolence 4y ago
I once read an article in Popular Science in the early 80's about the invention of quantum transistors at Texas Instruments. Are those what you mention?
- N1H1L 4y ago
  Not really. Our substrate today is silicon (really n-type silicon). We build a city on top of that substrate. Modern semiconductors have become way more heterogenous in recent years. Our gate insulators are not silicon dioxides anymore but high-k dielectrics such as hafnium oxide. And even interconnects now have different compositions, such as cobalt and copper. But the substrate is still holding us back, and one reason for that is creating high-quality single crystal wafers for silicon that are way more manageable. The solution for a long time has been to use direct bandgap semiconductors such as GaN, AlN, and so on. Silicon is an indirect bandgap semiconductor, meaning its conduction and valence bands are not aligned in momentum space. As a result, electrons hopping between these bands pay a thermal penalty. GaN and AlN don't have that problem, and we now have a plethora of crystals (especially complex oxides) that are all direct, and we have an entire library of bandgaps to choose from. The problem is that we cannot easily make wafers from these direct bandgap systems. At least yet to be on any commercial scale. Honestly, rather than flushing billions of dollars down the toilet for Zuck's vanity projects - we should have spent money to scale up Czochralski's growth[1] for a ton of crystal families. But, as we are reaching the limits for reticule sizes and we move to chiplet architectures, maybe smaller wafers will work too? [1] https://en.wikipedia.org/wiki/Czochralski_method https://en.wikipedia.org/wiki/Czochralski_method

m3kw9 4y ago

The compute size needed will likely move to cloud. What they need is lower wireless latency, deterministic speeds and reliability for that to happen.

pca006132 4y ago

It seems the bottleneck nowadays is mainly memory latency/throughput and thermo, the latter one is especially problematic for mobile devices due to less space for cooling. For memory, it seems that although we have higher throughput with DDR5, the latency is still high and we can only compensate it with larger cache, e.g. AMD 3D cache. For larger chips, you will get longer wires and may not be able to do things in 1 cycle. Assume that thermo is not an issue, you can probably cram many cores into 1 tiny chip, but the bus will probably be overloaded with too much traffic and long wire length. I think eventually cache coherency will be so expensive that we will go back to message passing for multicore or requires source/destination node ID for memory ordering...