There are a variety of 2.5D (chip next to chip) and 3D (chip on top of chip) packaging techniques. Each comes with different tradeoffs. Here are a couple of ar

There are a variety of 2.5D (chip next to chip) and 3D (chip on top of chip) packaging techniques. Each comes with different tradeoffs. Here are a couple of articles with more detailed info: https://semiwiki.com/semiconductor-manufacturers/tsmc/306329-advanced-2-5d-3d-packaging-roadmap/ https://semiwiki.com/semiconductor-manufacturers/tsmc/306329... https://www.anandtech.com/show/16051/3dfabric-the-home-for-tsmc-2-5d-and-3d-stacking-roadmap https://www.anandtech.com/show/16051/3dfabric-the-home-for-t... https://www.eetimes.com/amd-tsmc-imec-show-their-chiplet-playbooks-at-isscc/ https://www.eetimes.com/amd-tsmc-imec-show-their-chiplet-pla... https://www.techpowerup.com/292256/amd-details-its-3d-v-cache-design-at-isscc https://www.techpowerup.com/292256/amd-details-its-3d-v-cach...