4 ms·
Thanks. >I think there is some considerable signal/energy overhead to communicating between chips. I tried looking for some info on this but couldn't find any
by Vt71fcAqt7 4y ago
Thanks.
>I think there is some considerable signal/energy overhead to communicating between chips.
I tried looking for some info on this but couldn't find any. Do you have any source I could read on this?
- kayson 4y agoThis is a fundamental effect because of the Shannon-Hartley theorem[1], which says your communication channel's capacity (i.e. bitrate) has a log dependency on the channel's Signal to Noise Ratio. In a practical wireline communication system, you have a transmitter with noise, a lossy interconnect, and a receiver with noise. As the interconnect gets longer, which is what happens when you go from on-die communication to die-to-die communication, your loss increases. This means you have to reduce your transmitter and/or receiver noise which requires using additional power. Another way of looking at it is bit error rate [2]. I think you'll be hard-pressed to find concrete numbers since these designs are closely-guarded trade secrets. You might find some examples by searching for wireline transceiver / PHY papers on IEEE xplore, especially at ISSCC (conference) or in JSSCC (journal). [1] https://en.wikipedia.org/wiki/Shannon%E2%80%93Hartley_theorem https://en.wikipedia.org/wiki/Shannon%E2%80%93Hartley_theore... [2] https://en.wikipedia.org/wiki/Bit_error_rate https://en.wikipedia.org/wiki/Bit_error_rate