3 ms·

You get most of the economic value from the first few divisions. Going from 80% yield to 90% yield shaves 14% off your cost/unit. Going from 95% to 99% only sav

You get most of the economic value from the first few divisions. Going from 80% yield to 90% yield shaves 14% off your cost/unit. Going from 95% to 99% only saves you 4%. I'm not an expert at how they combine chips. Like I said for AMD, they also wanted their units to be composable w/ small number of chips, so they basically have a die w/ a few cores and different die w/ memory, and I believe they have a proprietary communication mesh for connecting them. I think there is some considerable signal/energy overhead to communicating between chips. The cost of masks and interconnects is probably high enough to make a high number of diverse chiplets inviable, but I wouldn't say it's impossible in the future.

Vt71fcAqt7 4y ago
Thanks. >I think there is some considerable signal/energy overhead to communicating between chips. I tried looking for some info on this but couldn't find any. Do you have any source I could read on this?
- kayson 4y ago
  This is a fundamental effect because of the Shannon-Hartley theorem[1], which says your communication channel's capacity (i.e. bitrate) has a log dependency on the channel's Signal to Noise Ratio. In a practical wireline communication system, you have a transmitter with noise, a lossy interconnect, and a receiver with noise. As the interconnect gets longer, which is what happens when you go from on-die communication to die-to-die communication, your loss increases. This means you have to reduce your transmitter and/or receiver noise which requires using additional power. Another way of looking at it is bit error rate [2]. I think you'll be hard-pressed to find concrete numbers since these designs are closely-guarded trade secrets. You might find some examples by searching for wireline transceiver / PHY papers on IEEE xplore, especially at ISSCC (conference) or in JSSCC (journal). [1] https://en.wikipedia.org/wiki/Shannon%E2%80%93Hartley_theorem https://en.wikipedia.org/wiki/Shannon%E2%80%93Hartley_theore... [2] https://en.wikipedia.org/wiki/Bit_error_rate https://en.wikipedia.org/wiki/Bit_error_rate

Vt71fcAqt7 4y ago

Thanks. >I think there is some considerable signal/energy overhead to communicating between chips. I tried looking for some info on this but couldn't find any. Do you have any source I could read on this?

kayson 4y ago
This is a fundamental effect because of the Shannon-Hartley theorem[1], which says your communication channel's capacity (i.e. bitrate) has a log dependency on the channel's Signal to Noise Ratio. In a practical wireline communication system, you have a transmitter with noise, a lossy interconnect, and a receiver with noise. As the interconnect gets longer, which is what happens when you go from on-die communication to die-to-die communication, your loss increases. This means you have to reduce your transmitter and/or receiver noise which requires using additional power. Another way of looking at it is bit error rate [2]. I think you'll be hard-pressed to find concrete numbers since these designs are closely-guarded trade secrets. You might find some examples by searching for wireline transceiver / PHY papers on IEEE xplore, especially at ISSCC (conference) or in JSSCC (journal). [1] https://en.wikipedia.org/wiki/Shannon%E2%80%93Hartley_theorem https://en.wikipedia.org/wiki/Shannon%E2%80%93Hartley_theore... [2] https://en.wikipedia.org/wiki/Bit_error_rate https://en.wikipedia.org/wiki/Bit_error_rate