Yeah. I've mentioned this before, but in DDR5 and beyond the nominal channel width goes from 64 bit to 32 bit -- and an ECC protected channel goes from 72 bit t

Yeah. I've mentioned this before, but in DDR5 and beyond the nominal channel width goes from 64 bit to 32 bit -- and an ECC protected channel goes from 72 bit to 40 bit. (It would be possible to ECC protect a 32-bit channel with 39 bits, but the actual DRAM ICs come in multiples of 8 bits.) This means that applications that bond channels together and read/write/ECC-check in 64-bit chunks can have 8 unassigned bits per 80-bit read, while still ECC protecting the full width. I haven't seen any discussion of this capability, but it's super interesting to me.