Here's MS driver model explaining that on a "GpuMmu" model driver, "Each process has separate CPU and GPU virtual address spaces that use distinct page tables":

Here's MS driver model explaining that on a "GpuMmu" model driver, "Each process has separate CPU and GPU virtual address spaces that use distinct page tables": https://learn.microsoft.com/en-us/windows-hardware/drivers/display/gpummu-model https://learn.microsoft.com/en-us/windows-hardware/drivers/d... Also the virtualization support advertised by NV and AMD uses this. Allowing for GPU partitioning, used eg in VDI setups. Eg NVidia seems to even have multiple generations of HW modes for this, one timeslicing based one (but I guess still HW enforced memory protection) and one core-splitting based one called MIG. And here's AMD in 2016: https://www.amd.com/system/files/documents/amd-mxgpu-white-paper.pdf https://www.amd.com/system/files/documents/amd-mxgpu-white-p... As usual with GPUs the problems seem to be more in the drivers and rest of sw stack, bugs, difficult programmability, proprietary nature, fragmentation, etc than strictly HW features.