4 ms·
At least with RISC-V you can always synthesize the core yourself in an fpga. It's vastly easier than it used to be and cheap fpga boards are becoming quite powe
by yummypaint 4y ago
At least with RISC-V you can always synthesize the core yourself in an fpga. It's vastly easier than it used to be and cheap fpga boards are becoming quite powerful. Something like the upduino board has a low barrier to entry. I'm particularly excited by the artix-7 line which also has open source toolchain support, though i haven't tried it myself yet.
Putting it in an fpga isn't as efficient as using the same area of silicon to make an asic, but for alot of applications it's totally fine. Plus you can actually hack on the architecture to suit your needs. An open and adaptable computing fabric that can be synthesized on demand sounds pretty disruptive to me.
- dinosaurdynasty 4y agoThis would be awesome if we had open and auditable FPGAs...
- synthos 4y agoCheck out OpenFPGA and RapidSilicon
- yummypaint 4y agoI know theoretically this is a problem, and I've heard people make similar statements, but I'm having a failure of imagination at thinking of specifics. If you are using a fully open source toolchain what does the threat model actually look like in the real world? Even if a device itself is malicious, what can it actually do to exfiltrate information about what's happening inside it without being incredibly obvious? How can it know what register bits are even of interest given some configuration bitstream? It just seems like there are so many hypotheticals that it isn't worth being concerned about. Would love to be educated about this.