3 ms·

Actually, we tend not to use PRBSs anymore for these sort of experiments, instead you use a randomly generated symbol/bit sequence which fits into the memory of

Actually, we tend not to use PRBSs anymore for these sort of experiments, instead you use a randomly generated symbol/bit sequence which fits into the memory of the DAC. Similarly you don't use a BERT anymore but instead use a Realtime oscilloscope (even more expensive than the BERTs) and do offline digital signal processing (in real systems this is done by very expensive asics). PRBSs and BERTs are still uses in so called datacom experiments where latency is often an issue and only very lightweight FEC is used, so one wants to measure down to error rates of 10e-9 unlike coherent systems.

jpmattia 4y ago
I find that interesting, and am curious: > instead you use a randomly generated symbol/bit sequence which fits into the memory of the DAC. How do you guarantee coverage of the entire spectrum? As I mentioned above, PRBS(N) has every bit sequence possible for N bits, which would expose any drop outs or resonances. > so one wants to measure down to error rates of 10e-9 unlike coherent systems. Back in the day, for OC-768 (40 Gbps/43 Gbps with FEC) equipment was measured to 10e-12. Has that relaxed? [IIRC, to gain 95% confidence that BER is 10e-9, you had to measure 10e10 bits. Similarly, for 95% confidence of BER 10e-12 you had to measure 10e13 bits. It's been a while though.]
- cycomanic 4y ago
  Very late reply so you might not see it. Modern systems use coherent (phase&amplitude and polarisation, typically QAM formats), together with relatively high overhead (~20%) FEC. The consequence is that for demonstration experiments you do offline processing, which significantly constrains how many bits you can measure (good experiments measure a few million per measurement point). So what people do is measure to the FEC threshold (10e-2) and assume the FEC works (usually a valid assumption). Sometimes people implement the FEC and show error free operation to 10e-6 or so. Also we use Generalized Mutual Information as a more accurate measure of the information content (it essentially measures how much information can be transmitted given a bitwise coding FEC). In other experiments people show FEC implementations running on banks of FPGAs to show that we actually get down to BER 10e-12, but these take weeks on large number of high end FPGAs.

jpmattia 4y ago

I find that interesting, and am curious: > instead you use a randomly generated symbol/bit sequence which fits into the memory of the DAC. How do you guarantee coverage of the entire spectrum? As I mentioned above, PRBS(N) has every bit sequence possible for N bits, which would expose any drop outs or resonances. > so one wants to measure down to error rates of 10e-9 unlike coherent systems. Back in the day, for OC-768 (40 Gbps/43 Gbps with FEC) equipment was measured to 10e-12. Has that relaxed? [IIRC, to gain 95% confidence that BER is 10e-9, you had to measure 10e10 bits. Similarly, for 95% confidence of BER 10e-12 you had to measure 10e13 bits. It's been a while though.]

cycomanic 4y ago
Very late reply so you might not see it. Modern systems use coherent (phase&amplitude and polarisation, typically QAM formats), together with relatively high overhead (~20%) FEC. The consequence is that for demonstration experiments you do offline processing, which significantly constrains how many bits you can measure (good experiments measure a few million per measurement point). So what people do is measure to the FEC threshold (10e-2) and assume the FEC works (usually a valid assumption). Sometimes people implement the FEC and show error free operation to 10e-6 or so. Also we use Generalized Mutual Information as a more accurate measure of the information content (it essentially measures how much information can be transmitted given a bitwise coding FEC). In other experiments people show FEC implementations running on banks of FPGAs to show that we actually get down to BER 10e-12, but these take weeks on large number of high end FPGAs.