3 ms·
It's just RISC-V. "RISC-V has been chosen as the instruction set architecture (ISA) for the SHAKTI class of processors. The SHAKTI processor and systems design
by chasil 4y ago
It's just RISC-V.
"RISC-V has been chosen as the instruction set architecture (ISA) for the SHAKTI class of processors. The SHAKTI processor and systems design is developed using the open source high-level synthesis (HLS) language: Bluespec System Verilog (BSV)."
- Pet_Ant 4y agoYes, but where is the actual Verilog for the cores? At least BlueSec doesn't seem to be a proprietary dialect: https://github.com/B-Lang-org/bsc https://github.com/B-Lang-org/bsc (BSD License)
- saidinesh5 4y agohttps://gitlab.com/shaktiproject/cores/ https://gitlab.com/shaktiproject/cores/ seems to have all the verilog they published.
- mhh__ 4y agoIf only it were that simple... (Saying it's "just" RISC-V is like saying the Clang is the same as same as hello world because they're both in C++)